Enhanced high speed performance from HDI thin film multi-chip modules

Publisher Website
Google Scholar
Abstract
A novel packaging technology, ideal for CMOS multichip modules, is described. Thin-film metal and polymer dielectric are used to fabricate five metal-layer structures with 25- mu m-wide traces and 11- mu m-thick dielectric layers. Features on the top pad layer can be fabricated to match the chip pads, allowing for orthogonal wire bonding with no fanout. In a microstrip configuration, the typical capacitance is 3.5 pF/in with a time of flight of about 160 ps/in. The propagation velocity (or phase velocity) for a sinusoidal wave is about 54% of the speed of light in vacuum. Multichip modules have been fabricated for applications ranging from two to 35 ICs, plus associated capacitors and resistors. With these features, the interconnect related propagation delay due to the capacitive loading or time of flight is in most cases less than the switching time of the driver gates (normally 1 ns). Low inductance power and ground planes are used throughout the module with on-board decoupling capacitors. Wire bonds on a 6-mil substrate pitch can be made routinely. The 6-mil pitch consists of a 4-mil pad and a 2-mil spacing between pads. With this pitch and short conductor lengths, bonding parasitics less than 1.2 nH are possible. Simultaneous switching noise is drastically reduced over conventional single-chip packaging methods.

This publication has 1 reference indexed in Scilit: