A BiCMOS channelless masterslice with on-chip voltage converter

13 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 176-177
https://doi.org/10.1109/isscc.1989.48248

Abstract

An approach to solving reliability problems due to voltage tolerance in submicron devices is described which involves lowering the operating voltage using an on-chip voltage conversion system. The masterslice has an on-chip voltage converter, TLL-compatible I/O circuits and uses advanced 0.8- mu m BiCMOS technology. A cross-sectional view of the BiCMOS device, which consists of CMOS transistors with simple n-well structure and an n-p-n bipolar transistor, is shown. The masterslice has been applied to a digital signal processing circuit. The chip contains 20 k gates, including four multiplier macrocells and random logic circuits. In the random logic circuits, which consist of double-size transistors, the packing density is 240 gate/mm/sup 2/, and the average delay is 600 ps for a two-input NAND gate with FO=3 and 1-mm wiring length. In the multipliers, 660 gate/mm/sup 2/ packing density and 450 ps average delay for 2-input NAND gate with FO=3 are attained.<>

Keywords

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