A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

1 January 1995

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits

Vol. 30 (12) , 1326-1332
https://doi.org/10.1109/4.482158

Abstract

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold- mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1- m BiCMOS technology, an experimental prototype exhibits a harmonic distortion of 65 dB with a 10-MHz analog input and occupies an area of 220 150 m The measured feedthrough is 52 dB for a 50-MHz analog input and the droop rate is 40 V/ns.

Keywords

This publication has 2 references indexed in Scilit:

BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A 10-b, 75-MHz two-stage pipelined bipolar A/D converter
IEEE Journal of Solid-State Circuits, 1993