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A transistor-level logic-with-timing simulator for MOS circuits
Home
Publications
A transistor-level logic-with-timing simulator for MOS circuits
A transistor-level logic-with-timing simulator for MOS circuits
TS
Thomas J. Schaefer
Thomas J. Schaefer
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1 January 1985
proceedings article
Published by
Association for Computing Machinery (ACM)
p.
762-765
https://doi.org/10.1145/317825.317982
Abstract
No abstract available
Cited
Cited by 4 articles
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