Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

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31 March 2004

journal article
research article
Published by Elsevier in Information Processing Letters

Vol. 89 (6) , 293-296
https://doi.org/10.1016/j.ipl.2003.12.007

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

Reduced complexity two-phase micropipeline latch controller
IEEE Journal of Solid-State Circuits, 1998
Receptive process theory
Acta Informatica, 1992
A formal model for defining and classifying delay-insensitive circuits and systems
Distributed Computing, 1986