Principal devices and hardware volume estimation for moving picture decoder for digital storage media

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Abstract
The ISO/MPEG has been discussing the establishment of a standard for moving- picture coding to ensure that digital storage media can store picture information efficiently. This paper introduces a trial design for the source decoder of simulation model 2 in the ISO/MPEG video subgroup. This paper describes MPEG simulation model decoding and the Fujitsu video signal processors, VSP-1 and DCT LSI chips. We designed a source decoder using these two LSI chips, memory, and standard logic ICs. The trial design showed that three VSP-ls and one DCT LSI chips are sufficient to make a source decoder.

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