Optimum load device for DMOS integrated circuits
- 1 August 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (4) , 443-452
- https://doi.org/10.1109/jssc.1976.1050757
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A high-speed logic LSI using diffusion self-aligned enhancement depletion MOSTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1975
- Threshold voltage controllability in double-diffused-MOS transistorsIEEE Transactions on Electron Devices, 1974
- Performance of refractory metal multilevel interconnection systemIEEE Transactions on Electron Devices, 1972
- D-MOS transistor for microwave applicationsIEEE Transactions on Electron Devices, 1972