30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

This publication has 3 references indexed in Scilit:

• CMOS devices below 0.1 μm: how high will performance go?
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Technology for advanced high-performance microprocessors
  IEEE Transactions on Electron Devices, 1998
• Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI
  IEEE Transactions on Electron Devices, 1995