The concept and initial studies of a crosstie random access memory (CRAM)

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Abstract
The crosstie‐Bloch line memory elements which were used in the serial crosstie memory can be reconfigured into a random access memory. The new approach decreases the access time, eliminates complexity, increases reliability, and is straightforward. The five‐level nonvolatile device is intended to be integrated on a silicon chip with decoders and drivers on the chip. It is expected that some of the five levels will be folded in with the levels used to connect the transistors needed for decoding and driving.

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