Concurrent error detection and testing for large PLA's

1 April 1982

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 29 (4) , 756-764
https://doi.org/10.1109/T-ED.1982.20774

Abstract

A system of checkers is designed for concurrent error detection in large PLA's. This system combines concurrent error detection with off-line functional, testing of the PLA by using the same checker hardware for both purposes. The result is a significant saving in hardware cost. For a case example, the total hardware cost is estimated at about 37 percent of the original PLA area. The system is almost totally self-checking and, although the test patterns are not function-independent, their generation algorithm is simple. The total test time for the entire system is within the range of that of some recent PLA design schemes which were specifically aimed at simplifying off-line testing, but which have no provisions for concurrent error detection.

Keywords

This publication has 0 references indexed in Scilit: