A 1.3 GHz fifth generation SPARC64 microprocessor
- 22 December 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1 (01936530) , 246-491
- https://doi.org/10.1109/isscc.2003.1234286
Abstract
A fifth generation SPARC64 processor implemented in 130 nm CMOS process with 8 layers of Cu metallization operates with a 1.3 GHz clock and dissipates 34.7 W. The processor is a 4-issue out-of-order design with 2 MB on-chip level-2 cache. Error checking is added on the data-path in addition to memory. An instruction is retried for correction when an error is detected in the datapath.Keywords
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