Design of high performance PFETs with strained si channel and laser anneal
- 6 April 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 241 (01631918) , 489-492
- https://doi.org/10.1109/iedm.2005.1609388
Abstract
The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyondKeywords
This publication has 1 reference indexed in Scilit:
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