An encoder/decoder chip set for the MPEG video standard

1 January 1992

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 5, 661-664 vol.5
https://doi.org/10.1109/icassp.1992.226509

Abstract

A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using three chips, an MPEG video encounter can compress a 30-frames/s image sequence of 352 pels*240 lines. A decoder can be constructed with two chips for the same sequence.<>

Keywords

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