A boosted dual world-line decoding scheme for 256 Mb DRAMs

Abstract
A boosted dual word-line decoding scheme with regulated power supply is developed to realize a memory cell applicable to 256 Mb DRAMs by using silicon dioxide as a dielectric material, and without area increase of the memory cell array. The scheme relaxes the wiring pitch on the cell array, thus making it easier to realize wiring patterns in the large step environment caused by the stack capacitor thickness. A capacitance of up to 50 fF can be realized for a dual cylindrical structure with 1 mu m height and 5 mm oxid thickness. The scheme yields word rising operations two times faster than conventional approaches.

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