Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction

20 September 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1
https://doi.org/10.1109/iscas.2004.1328384

Abstract

This work presents a system level model of the clock jitter influence in certain types of continuous time sigma delta modulators. The model helps the design of such modulators by speeding up the simulations, predicting analytically the SNR degradation and providing a practical way to minimize the jitter sensitivity of the modulator. Simulations and theoretical developments are contrasted with measurements in a real chip.

Keywords

DELTA-SIGMA MODULATION
DELTA MODULATION
CLOCKS
JITTER
NOISE REDUCTION
PREDICTIVE MODELS
ANALYTICAL MODELS
SIGNAL TO NOISE RATIO
DEGRADATION
SEMICONDUCTOR DEVICE MEASUREMENT

This publication has 1 reference indexed in Scilit:

Behavioral modeling of switched-capacitor sigma-delta modulators
IEEE Transactions on Circuits and Systems I: Regular Papers, 2003