An analytical thermal noise model of deep submicron MOSFET's
- 1 August 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 20 (8) , 399-401
- https://doi.org/10.1109/55.778156
Abstract
An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur.Keywords
This publication has 8 references indexed in Scilit:
- Compact MOS modeling for analog circuit simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An improved analytical LDD-MOSFET model for digital and analog circuit simulation for all channel lengths down to deep-submicronPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low noise FET design for wireless communicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- RauschenPublished by Springer Nature ,1990
- High-frequency noise measurements on FET's with small dimensionsIEEE Transactions on Electron Devices, 1986
- Physics of the MOS TransistorPublished by Elsevier ,1981
- Effects of intervalley scattering on noise in GaAs and InP field-effect transistorsIEEE Transactions on Electron Devices, 1976
- DIFFUSIVITY OF ELECTRONS AND HOLES IN SILICONApplied Physics Letters, 1969