Latchup free CMOS using guarded Schottky barrier PMOS

• 1 January 1984
• proceedings article
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• https://doi.org/10.1109/iedm.1984.190735

Abstract

Keywords

• NUMERICAL SIMULATION
• VERY LARGE SCALE INTEGRATION
• FABRICATION
• CMOS TECHNOLOGY
• BIPOLAR TRANSISTORS
• BIPOLAR TRANSISTOR
• SCHOTTKY BARRIER