A pipelined 9-stage video-rate analog-to-digital converter
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 26.4/1-26.4/4
- https://doi.org/10.1109/cicc.1991.163994
Abstract
The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9- mu m CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm/sup 2/ and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures.<>Keywords
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