VLSI implementation of a maximum-likelihood decoder for the Golay (24, 12) code
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal on Selected Areas in Communications
- Vol. 6 (3) , 558-565
- https://doi.org/10.1109/49.1924
Abstract
J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three-μm NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 μs. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallelKeywords
This publication has 2 references indexed in Scilit:
- Soft decoding techniques for codes and lattices, including the Golay code and the Leech latticeIEEE Transactions on Information Theory, 1986
- An Efficient Algorithm for Soft-Decision Decoding of the (24, 12) Extended Golay CodeIEEE Transactions on Communications, 1981