A deterministic algorithm for automatic CMOS transistor sizing
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (2) , 522-526
- https://doi.org/10.1109/4.1017
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- Delay-time evaluation in ED MOS logic LSIIEEE Journal of Solid-State Circuits, 1986