Eliminating operand read latency

1 December 1996

journal article
Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News

Vol. 24 (5) , 18-22
https://doi.org/10.1145/242694.242708

Abstract

Programs generally exhibit load or memory operand read latencies that account for a significant portion of pipeline interlocks or stalls. In this paper we present an approach for the prediction of operand read data during the instruction fetch stage of a pipelined processor. For the X86 programs studied many have a significant percentage of such operand data that can be predicted with a high accuracy.

Keywords

LATENCIES
READ LATENCY
OPERAND READ
INSTRUCTION
STALLS
PROCESSOR
MEMORY
FETCH

This publication has 2 references indexed in Scilit:

Streamlining data cache access with fast address calculation
Published by Association for Computing Machinery (ACM) ,1995
Techniques for compressing program address traces
Published by Association for Computing Machinery (ACM) ,1994