Two-dimensional optical interconnect between CMOS IC's

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Abstract
The central issue of optically interconnected integrated circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers throughput data interconnects on inter-chip and MCM level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-of-the-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 pm pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, components, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-D architecture, conceptually consisting of a number of electronic planes (electrical FPGAs), that are interconnected bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8/spl times/8 array of simple configurable logic blocks (a 4-bit function table, one flip-flop), interconnected by a programmable 6-6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8/spl times/8 source arrays (either LEDs or VCSELs) and two 8/spl times/8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbit/s. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8/spl times/16 POF ribbons. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive alignment of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements are discussed.

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