Design of VLSI implemented signal processing systems based on signal flow graph analyses
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1947-1951
- https://doi.org/10.1109/iscas.1988.15320
Abstract
An efficient design approach based on signal flow graph (SFG) analyses is introduced. A common set of VLSI structures has been derived for homogeneous and shuffle-exchange SFGs and are shown to be applicable to a general set of signal processing algorithms. The feasibility of this SFG-oriented design approach is demonstrated by an efficient implementation of the convolutional encoder/decoder, which is a significant achievement for coding system design.<>Keywords
This publication has 9 references indexed in Scilit:
- A look-up table VLSI design methodology for RNS structures used in DSP applicationsIEEE Transactions on Circuits and Systems, 1987
- Flowgraph analysis of large electronic networksIEEE Transactions on Circuits and Systems, 1986
- VLSI implementation of two-dimensional digital filters via two-dimensional filter chipsIEEE Transactions on Circuits and Systems, 1986
- Architectures for VLSI implementation of movement-compensated video processorsIEEE Journal of Solid-State Circuits, 1986
- VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmeticIEEE Transactions on Circuits and Systems, 1986
- Contributions to the application of the Viterbi algorithmIEEE Transactions on Information Theory, 1985
- A radix 4 delay commutator for fast Fourier transform processor implementationIEEE Journal of Solid-State Circuits, 1984
- Convolutional codes II. Maximum-likelihood decodingInformation and Control, 1974
- The viterbi algorithmProceedings of the IEEE, 1973