An analog neural network processor for self-organizing mapping
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 136-137,
- https://doi.org/10.1109/isscc.1992.200449
Abstract
The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2- mu m CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.<>Keywords
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