Fourteen ways to fool your synchronizer
- 8 October 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2001 (15228681) , 89-96
- https://doi.org/10.1109/async.2003.1199169
Abstract
Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.Keywords
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