CMOS pipelined A/D convertor using current divider

28 September 1989

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 25 (20) , 1341-1343
https://doi.org/10.1049/el:19890896

Abstract

A novel dynamic current divider based¹ CMOS pipelined A/D convertor principle is presented. A basic successive approximation scheme is applied, thus the signal is not modified (i.e successively multiplied by two) along the A/D conversion. Consequently the most important speed limitation is the time to achieve the successive comparisons, which is lower than the time for signals to settle within 1/2 LSB in multiplying schemes^2.3

Keywords

SPEED LIMITATION
CONVERTOR
CMOS PIPELINED
CURRENT DIVIDER
SUCCESSIVE APPROXIMATION SCHEME

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