Pipelined memory shared buffer for VLSI switches
- 1 October 1995
- proceedings article
- Published by Association for Computing Machinery (ACM)
- Vol. 25 (4) , 39-48
- https://doi.org/10.1145/217382.217406
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- A flexible shared-buffer switch for ATM at Gbs ratesComputer Networks and ISDN Systems, 1995
- Two-dimensional round-robin schedulers for packet switches with multiple input queuesIEEE/ACM Transactions on Networking, 1994
- High-speed switch scheduling for local-area networksACM Transactions on Computer Systems, 1993
- Analysis of input and output queueing for nonblocking ATM switchesIEEE/ACM Transactions on Networking, 1993
- Symmetric crossbar arbiters for VLSI communication switchesIEEE Transactions on Parallel and Distributed Systems, 1993
- 32*32 shared buffer type ATM switch VLSIs for B-ISDNsIEEE Journal on Selected Areas in Communications, 1991
- A one-chip scalable 8*8 ATM switch LSI employing shared buffer architectureIEEE Journal on Selected Areas in Communications, 1991
- Weighted round-robin cell multiplexing in a general-purpose ATM switch chipIEEE Journal on Selected Areas in Communications, 1991
- The design of nectar: a network backplane for heterogeneous multicomputersACM SIGARCH Computer Architecture News, 1989
- The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet SwitchingIEEE Journal on Selected Areas in Communications, 1987