DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 42 (10) , 1871-1872
- https://doi.org/10.1109/16.464405
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A 1.5 V DRAM for battery-based applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- UV-O/sub 3/ and dry-O/sub 2/: Two-step-annealed chemical vapor-deposited Ta/sub 2/O/sub 5/ films for storage dielectrics of 64-Mb DRAMsIEEE Transactions on Electron Devices, 1991
- Conduction Mechanism of Leakage Current in Ta2 O 5 Films on Si Prepared by LPCVDJournal of the Electrochemical Society, 1990
- Preparation and Properties of Ta2 O 5 Films by LPCVD for ULSI ApplicationJournal of the Electrochemical Society, 1990
- Two-step annealing technique for leakage current reduction in chemical-vapor-deposited Ta/sub 2/O/sub 5/ filmIEEE Electron Device Letters, 1989
- Oxidized Ta/sub 2/O/sub 5//Si/sub 3/N/sub 4/ dielectric films on poly-crystalline Si for dRAMsIEEE Transactions on Electron Devices, 1989
- A high quality high temperature compatible Tantalum oxide film for advanced dRAM applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987