Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations
- 1 September 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (5) , 848-862
- https://doi.org/10.1109/tcad.1987.1270328
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- Managing VLSI complexity: An outlookProceedings of the IEEE, 1983
- Hierarchical design methodologies and tools for VLSI chipsProceedings of the IEEE, 1983
- VISTA: A VLSI CAD SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
- An Experimental Delay Test Generator for LSI LogicIEEE Transactions on Computers, 1980
- High-speed concurrent fault simulation with vectors and scalarsPublished by Association for Computing Machinery (ACM) ,1980
- Part II: Logic circuit simulationIEEE Circuits & Systems Magazine, 1979
- Hierarchical Modeling and Simulation in VISTAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A New Representation for Faults in Combinational Digital CircuitsIEEE Transactions on Computers, 1972
- Fault Equivalence in Combinational Logic NetworksIEEE Transactions on Computers, 1971
- Test Routines Based on Symbolic Logical StatementsJournal of the ACM, 1959