Interconnect IP node for future system-on-chip designs
- 25 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An interconnect IP (intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for the on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks, which include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture properly.Keywords
This publication has 3 references indexed in Scilit:
- Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Stream communication between real-time tasks in a high-performance multiprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Addressing the system-on-a-chip interconnect woes through communication-based designPublished by Association for Computing Machinery (ACM) ,2001