Deep trench isolated CMOS devices

1 January 1982

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 237-240
https://doi.org/10.1109/iedm.1982.190261

Abstract

A deep (5-6 microns) trench isolation process which permits minimum feature size spacing between n- and p-channel devices in bulk CMOS is described. Susceptibility to latch-up at 1.2 microns n-p spacing is reduced (relative to a standard process) or eliminated using a comparatively easy epitaxial process. The trench process is dislocation free and has been used for nonencroaching device isolation. Trench-bounded n- and p-channel devices show good characteristics down to submicron effective channel lengths, and completely trench isolated ring oscillators have been built and tested. Further development effort will go toward controlling the influence of trench sidewall parasitic channels adjacent to n-channel devices.

Keywords

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