TRACER-fpga: a router for RAM-based FPGA's
- 1 March 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 14 (3) , 371-374
- https://doi.org/10.1109/43.365127
Abstract
We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulationKeywords
This publication has 3 references indexed in Scilit:
- A new global router for ASIC design based on simulated evolutionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A detailed router for field-programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An Algorithm for Path Connections and Its ApplicationsIEEE Transactions on Electronic Computers, 1961