On the parasitic capacitances of multilevel parallel metallization lines

1 November 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 32 (11) , 2408-2414
https://doi.org/10.1109/T-ED.1985.22287

Abstract

A versatile and powerful finite-difference solution technique is developed for determining the capacitances between arrays of closely spaced parallel conductors. Results are presented for configurations typical of multilevel VLSI structures.

Keywords

CONDUCTORS
HYDROGEN
SPARSE MATRICES
FINITE ELEMENT METHODS
PERMITTIVITY
METALLIZATION
DIELECTRICS
VERY LARGE SCALE INTEGRATION
FINITE DIFFERENCE METHODS
MICROELECTRONICS
PARASITIC CAPACITANCE
INTEGRAL EQUATIONS

This publication has 0 references indexed in Scilit: