Thermal impedance of ceramic packages using beam-lead IC chips

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Abstract
A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calculating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following mounting conditions: a) package with external leads heat-sinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on Al2O3substrate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the substrate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels.

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