A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A pipelined interpolating ADC which employs a chopper inverter amplifier capable of operating at low supply voltage is described. The DNL (differential nonlinearity) is less than +or-0.5 LSB at 20-MHz conversion frequency. The signal-to-noise and distortion ratio is 55 dB at 1 MHz for a 2 V pp analog input. The INL (integral nonlinearity) is less than +or-1.0 LSB. This ADC dissipates 30 mW with 2.5-V single supply at a 20-MHz conversion rate. The active area is 2.5 mm*2.6 mm in 0.8- mu m CMOS. The input capacitance is 12 pF.<>Keywords
This publication has 2 references indexed in Scilit:
- A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A Technique For Reducing Differential Non-linearity Errors In Flash A/D ConvertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991