Programmable analog vector-matrix multipliers
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (1) , 207-214
- https://doi.org/10.1109/4.50305
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- A programmable analog neural network chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Programmable vector-matrix multipliers for artificial neural networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Cascadable 32*32 vector-matrix multiplier for artificial neural networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Design of parallel hardware neural network systems from custom analog VLSI 'building block' chipsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Architecture for large microelectronic supervised learning artificial neural networks using a hybrid digital-analog approachNeural Networks, 1988
- A ±5-V CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1987
- Analogue circuits for variable-synapse electronic neural networksElectronics Letters, 1987
- A CMOS associative memory chip based on neural networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A 20-V four-quadrant CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1985
- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982