Improved systolic array for linear discriminant function classifier

16 January 1986

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 22 (2) , 85-86
https://doi.org/10.1049/el:19860058

Abstract

A word-level systolic array with 100% efficiency is described for the linear discriminant function classifier. When compared with two previous word-level linear classifier arrays, it not only saves about C inner product step cells, where C is the number of weighted vectors used, but also simplifies the chip's I/O design.

Keywords

I/O DESIGN
PATTERN RECOGNITION
WEIGHTED VECTORS
WORD-LEVEL SYSTOLIC ARRAY
LINEAR DISCRIMINANT FUNCTION CLASSIFIER

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