A 100 MHz macropipelined CISC CMOS microprocessor

2 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 104-105
https://doi.org/10.1109/isscc.1992.200433

Abstract

A macropipelined CISC microprocessor implemented in a 0.75- mu m CMOS 3.3-V three-metal-layer technology is described. The 1.3 M-transistor custom chip measures 1.62*1.46 cm/sup 2/, dissipates 18 W (peak), and is packaged in a 339-pin PGA. The chip implements a macroinstruction pipeline to execute the instruction set of a popular CISC minicomputer. A block diagram of the major functional units is shown along with die micrograph.<>

Keywords

MICROPROCESSORS
CLOCKS
DECODING
ROUTING
DELAY
CMOS TECHNOLOGY
SEMICONDUCTOR DEVICE MEASUREMENT
READ ONLY MEMORY
FLIP-FLOPS
SWITCHES

This publication has 1 reference indexed in Scilit:

CMOS implementation of a 32 b computer
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003