Linear placement algorithms and applications to VLSI design

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Abstract
A linear placement technique that uses an objective function of the sum of wiring lengths is proposed. The method evolves from well‐known concepts in job sequencing and network flow. The relation between a job sequencing problem and this linear placement problem was demonstrated by Lawler. Also, Sidney proposed decomposition algorithms for job sequencing problems. Building on Lawler's and Sidney's work, we first develop a polynomial‐time algorithm to obtain optimal solutions for the special case of parallel graphs. Adolphson and Hu applied the max‐flow min‐cut method of the network flow problem to the partitioning of general placement problems. However, when the cut operation creates the cut of the same configuration as the previous cut operations, no additional partitioning information is obtained. We devise an optimal graph modification that tries to change the configuration of the cut for further partitioning of the problem, and achieve the maximum partitioning of the problem. Finally, a heuristic algorithm is derived to solve some Very Large Scale Integrated Circuits (VLSI) design linear placement problems. A comparison with published papers shows that our VLSI placement method produces better results.

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