Test Generation for Highly Sequential Circuits

Abstract
We address the problem of generating test sequences for stuck-at faults in non-scan synchronous sequential circuits. We present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, we decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. We describe fast algorithms for state justification and state differentiation using the ON-sets and OFF-sets of flip-flop inputs and primary outputs. The decomposition of the testing problems into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault free rather than the faulty machine and the use of efficient techniques for cube intersection results in significant performance improvements over previous approaches.

This publication has 0 references indexed in Scilit: