A scarce-state-transition Viterbi-decoder VLSI for bit error correction
- 1 August 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (4) , 575-582
- https://doi.org/10.1109/jssc.1987.1052775
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- A single-chip 80-bit floating point processorIEEE Journal of Solid-State Circuits, 1985
- An Integrated Modular and Standard Cell VLSI Design ApproachIEEE Journal of Solid-State Circuits, 1985
- CHAMP: Chip Floor Plan for Hierarchical VLSI Layout DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- New syndrome decoding techniques for the (n,k) convolutional codesIEE Proceedings F Communications, Radar and Signal Processing, 1984
- A monolithic CMOS maximum-likelihood convolutional decoder for digital communication systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Hierarchical top-down layout design method for VLSI chipPublished by Association for Computing Machinery (ACM) ,1982
- Syndrome Decoding of Binary Rate-1/2 Convolutional CodesIEEE Transactions on Communications, 1976
- Convolutional Codes and Their Performance in Communication SystemsIEEE Transactions on Communication Technology, 1971
- Viterbi Decoding for Satellite and Space CommunicationIEEE Transactions on Communication Technology, 1971