A programmable image processing system using FPGAs
- 1 October 1993
- journal article
- vlsi circuits-and-systems
- Published by Taylor & Francis in International Journal of Electronics
- Vol. 75 (4) , 725-730
- https://doi.org/10.1080/00207219308907150
Abstract
Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.Keywords
This publication has 3 references indexed in Scilit:
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- VLSI median filtersIEEE Transactions on Acoustics, Speech, and Signal Processing, 1990
- Design and implementation of a single-chip 1-D median filterIEEE Transactions on Acoustics, Speech, and Signal Processing, 1983