Nonlinear JFET model for computer-aided circuit analysis
- 1 February 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 6 (1) , 55-56
- https://doi.org/10.1109/JSSC.1971.1050158
Abstract
A simplified circuit model is proposed to represent the nonlinear d.c. and low-frequency small-signal operation of j.f.e.t.s. This model is particularly useful for computer-aided circuit analysis programs, such as the iterative nodal analysis program BIAS-3. Operation in the off, resistance, and pinch-off regions of the j.f.e.t. is included.Keywords
This publication has 3 references indexed in Scilit:
- BIAS-3-A program for the nonlinear D.C. analysis of bipolar transistor circuitsIEEE Journal of Solid-State Circuits, 1971
- A simple derivation of field-effect transistor characteristicsProceedings of the IEEE, 1963
- The silicon insulated-gate field-effect transistorProceedings of the IEEE, 1963