A comparative study of CMOS processes for VLSI applications

1 October 1982

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 29 (10) , 1593-1598
https://doi.org/10.1109/t-ed.1982.20919

Abstract

A comparative study of simulated circuit performance has been made in order to determine the optimum process parameters for p-well CMOS with feature sizes of between 1 and 2 µm. it has been found that for the process considered, best speed, Power, and packing density are achieved with a substrate concentration of between 3 × 1015and 1016cm-3and an operating voltage which is as low as possible. Higher speed can be attained at the expense of considerably more power dissipation through the use of a higher rail voltage. Silicon-on-insulator CMOS has been considered as an alternative to p-well CMOS. This technology can be expected to out-perform small geometry bulk silicon CMOS if recent improvements in material quality can be maintained.

Keywords

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