A flexible motion-vector estimation chip for real-time video codecs

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Abstract
The implementation of a versatile full-search block-matching motion estimation chip is described. This chip calculates a motion vector for a block, with a block size of 8*8, 16*16, or 32*32, and outputs the minimum block difference and the block difference of no motion. This chip is one of the most computationally intensive building modules in a video codec. A novel data flow design is reviewed, which allows sequential inputs and performs parallel processing with 100% efficiency. Implementation of this chip is targeted at high performance for real-time video compression. An optimization of the processing elements was performed using pipeline architecture to reduce the cycle time. Each comparison performed in the comparator module was distributed into two cycles to avoid speed bottleneck. Testing circuitry was included to reduce the huge testing patterns. The implementation was carried out by using 1 mu m CMOS technology. Simulation showed that 30 MHz operation can be achieved.

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