AT/sup 2/-optimal Galois field multiplier for VLSI
- 1 January 1989
- journal article
- letter
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 38 (9) , 1333-1336
- https://doi.org/10.1109/12.29475
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- Area-time optimal division for T = Ω((log n)1 + ε)Information and Computation, 1987
- Log Depth Circuits for Division and Related ProblemsSIAM Journal on Computing, 1986
- VLSI Architectures for Computing Multiplications and Inverses in GF(2m)IEEE Transactions on Computers, 1985
- Logarithmic depth circuits for algebraic functionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Area—Time optimal VLSI integer multiplier with minimum computation timeInformation and Control, 1983
- The Area-Time Complexity of Binary MultiplicationJournal of the ACM, 1981
- Area-time complexity for VLSIPublished by Association for Computing Machinery (ACM) ,1979
- Schnelle Multiplikation von Polynomen ber K rpern der Charakteristik 2Acta Informatica, 1977
- Schnelle Multiplikation großer ZahlenComputing, 1971
- Coding TheoryLecture Notes in Mathematics, 1971