Gate delays of InGaAs/InP heterojunction integrated injection logic
- 1 August 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 3 (8) , 200-202
- https://doi.org/10.1109/edl.1982.25550
Abstract
The delay time of an InGaAs/InP heterojunction bipolar transistor integrated injection logic gate is calculated as a function of the npn transistor upward current gain and for fan-outs of one and four. It is shown that intrinsic gate delays under 300 psec are possible with a fan-out of 4 for a gate designed with 3 µm design rules and having 0.5 µm npn and pnp base widths. Gate delays well under 100 psec are predicted for less conservative designs.Keywords
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