On a Bit-Serial Input and Bit-Serial Output Multiplier
- 1 September 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-32 (9) , 878-880
- https://doi.org/10.1109/tc.1983.1676341
Abstract
A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.Keywords
This publication has 4 references indexed in Scilit:
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- On-Line Algorithms for Division and MultiplicationIEEE Transactions on Computers, 1977
- The Two's Complement Quasi-Serial MultiplierIEEE Transactions on Computers, 1975
- The Quasi-Serial MultiplierIEEE Transactions on Computers, 1973