Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip
- 22 December 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320x240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.Keywords
This publication has 3 references indexed in Scilit:
- Hardware/software partitioning of embedded system in OCAPI-xlPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Preemptive multitasking on FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2000
- Partitioning tasks between a pair of interconnected heterogeneous processors: A case studyConcurrency: Practice and Experience, 1995