More wires and fewer LUTs

1 January 1998

proceedings article
Published by Association for Computing Machinery (ACM)

p. 12-19
https://doi.org/10.1145/275107.275113

Abstract

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.

Keywords

DEV ELOPING WELL-BALANCED FPGAS
ARCHITECTURE-DECISION PROCESS
LOGIC BLOCK
W E PRESEN
EFFECTIV E
FEWER LUTS
WELL-BALANCED FPGA ARCHITECTURE
NEW FPGA
LOOK-UP TABLES
FPGA DESIGN METHODOLOGY
FPGA DEVELOPMENT
PROGRAMMABLE LOGIC
ROUTING
DESIGN METHODOLOGY
LOOK UP TABLE
FPGA

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